Field of the Invention
The present invention relates generally to measuring leakage current from capacitors in integrated circuits, and more particularly, to the measurement of different types of leakage current from deep trench capacitors in dynamic random access memory (DRAM) cells.
The accurate measurement of DRAM cell capacitor leakage is an important technique for evaluating the retention time of the DRAM cells. This measurement becomes increasingly important with the scaling of memory technology by the reduction of storage capacitance and stored charge.
In a deep-trench capacitor structure (e.g, in FIG. 3), there are two major components of leakage current. One component is the buried strap leakage current (IBS) which is dominated by the pn junction leakage. The other component is the nitride-oxide (NO) film leakage current, sometimes referred to as the deep trench leakage current, (IDT) which is dominated by Frenkel-Poole emission. Conventionally, it is difficult to distinguish between these two leakage currents, IBS and IDT.
Very small resistances, and thus leakage currents, can be measured by the circuit arrangement shown in FIG. 1. This arrangement is for measuring resistance in a simple three terminal device having internal resistances R1, R2, and R3. For example, as in FIG. 1, R2 is connected to ground, R3 is connected to a virtual ground at differential amplifier 10, and a known input voltage VIN is applied to R1. The voltage output by the differential amplifier 10 can be used to calculate R1, R2, and R3. However, this simple resistance measurement technique is only of use when the three terminal device has a similarly simple resistance structure as shown in FIG. 1.
However, the DRAM structure of interest, shown schematically in FIG. 2, includes a deep trench resistance 40 (RDT), a large substrate resistance 50 (Rsub), and a buried plate resistance 30 (Rbp). Further, as FIG. 2 shows, the storage node (SN), substrate (SUB), and buried plate (BP) measurement points are common to many DRAM cells, resulting in a very complex resistance structure. Therefore, a conventional current measurement useful with the simple R1, R2, and R3 resistance structure shown in FIG. 1 is not appropriate for the complex resistance structure shown in FIG. 2. In the conventional 3-terminal measurement, the current flow (I13) from the node 1 to node 3 through the resistor R1 and R3 will be measured from the node 3. The current flow (I23) from the node 2 to node 3 will be equal to zero induced be the true ground (node 2) and virtual ground (node 3). Then we can get the current flow of node to node for the 3-terminal structure.
But in the DRAM cell with deep trench capacitor structure, the substrate resistance and buried plate resistance are the distributed resistance. The 3-terminal structure of storage node, substrate and buried plate is not a simple R1, R2, and R3 structure any more. If we set the true ground node at the buried plate (BP) and virtual ground node at substrate (SUB), the current measured from the SUB node will include the ISN-SUB through the substrate resistor (Rsub) and the (IDT-BP-SUB) through the trench capacitor resistor (Rdt) and buried plate resistor (Rbp). That is not what we want. Also, the large areas of the substrate and buried plate induce a noise effect which further complicates this resistance measurement. Thus, the simple resistance measurement method outlined above is not suitable for DRAM cell leakage measurement.
The buried strap leakage current is dominated by the pn junction current dependent upon temperature, and the NO film leakage current is also dependent on temperature. Thus, the two leakage currents are unable to be decoupled by temperature.
When such deep trench capacitors are scaled to a smaller size, their capacitance must be increased by reducing the thickness of the NO film. In such an event, the NO film leakage can increase to be comparable in magnitude with the buried strap leakage current. It is useful for DRAM circuit designers to know how the NO film leakage current has increased due to their designs.
A method of accurately determining both the buried strap and the NO film leakage current during wafer testing enable the estimation of DRAM cell behavior before product testing begins. Because leakage current is an important design characteristic of DRAM cells, it is very important to know accurately where the leakage occurs, either through buried strap leakage or NO film leakage.
The objects of the invention are to measure different leakage currents from the same node under different biasing conditions, thereby reducing a noise effect induced by the large substrate and buried plate. A new testing procedure is provided, used in, for example, wide area testing (WAT), during integrated circuit manufacturing to measure buried strap and deep trench capacitor leakage currents.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, an embodiment of the invention includes a method for measuring buried strap leakage current in a capacitor having one plate electrically connected to a source terminal of a transistor and having a buried plate, the transistor further having a gate terminal and a substrate terminal, the method comprising: applying a biasing voltage to the substrate terminal of the transistor; applying a sweep voltage to the source terminal of the transistor and to the buried plate of the capacitor; and measuring the buried strap leakage current at the source terminal of the transistor.
Another embodiment of the invention includes a method for measuring deep trench leakage current in a capacitor having one plate electrically connected to a source terminal of a transistor and having a buried plate, the transistor further having a gate terminal and a substrate terminal, the method comprising: obtaining a buried strap leakage current value for the capacitor corresponding to a diode voltage between the source terminal and the substrate terminal; applying a biasing voltage to the buried plate of the capacitor; applying a first sweep voltage to the substrate terminal of the transistor; applying a second sweep voltage to the source terminal of the transistor equal to a sum of the first sweep voltage and the diode voltage; measuring a current at the source terminal of the transistor; and subtracting the buried strap leakage current value from the measured current to obtain the deep trench leakage current.
Still another embodiment of the invention includes a method for measuring deep trench leakage current in a capacitor having one plate electrically connected to a source terminal of a transistor and having a buried plate, the transistor further having a gate terminal and a substrate terminal, the method comprising: obtaining a buried strap leakage current for the capacitor; applying a biasing voltage to the buried plate of the capacitor; applying a diode voltage to the substrate terminal of the transistor; applying a sweep voltage to the source terminal of the transistor; measuring a current at the source terminal of the transistor; and subtracting the buried strap leakage current from the measured current to obtain the deep trench leakage current.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.